Reliability of Al2O3/In-Si-O-C Thin-Film Transistors with an Al2O3 Passivation Layer under Gate-Bias Stress. (23rd July 2018)

• Record Type: Journal Article
• Authors: Kurishima, Kazunori; Nabatame, Toshihide; Onaya, Takashi; Tsukagoshi, Kazuhito; Ohi, Akihiko; Ikeda, Naoki; Nagata, Takahiro; Ogura, Atsushi
• Is Part Of: ECS transactions. Volume 86:Number 11(2018)
• Page Start: 135
• Page End: 145
• Publication Date: 2018-07-23
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08611.0135ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We investigated relationship between threshold voltage shift (Δ V th ) and hole and deep traps at Al2 O3 insulator/In-Si-O-C interface for In-Si-O-C thin-film transistors (TFTs) with Al2 O3 dielectric using an Al2 O3 passivation layer under the negative gate bias stress (NBS) and negative gate bias illumination stress (NBIS) conditions. A large Δ V th of -4.7 V was observed in TFT without an Al2 O3 passivation layer (w/o) due to the three components such as hole trap (-0.9 V) at around the valence band edge, deep trap (-0.7 V) and hole trap (-3.1 V) at around fermi-level generated by absorbed O2 molecule at Al2 O3 insulator/In-Si-O-C interface. The influence of absorbed O2 molecule on Δ V th could be significantly suppressed up to approximately 45 % as an Al2 O3 passivation layer increases from 0 to 10 nm.