Increase in Oxide Trap Density Due to the Implementation of High-k and Al2O3 Cap Layers in Thick-Oxide Input-Output Transistors for DRAM Applications. (14th September 2015)

• Record Type: Journal Article
• Authors: Simoen, Eddy; Ritzenthaler, Romain; Cho, Moon Ju; Schram, Tom; Horiguchi, Naoto; Aoulaiche, Marc; Spessot, Alessio; Fazan, Pierre; Claeys, Cor
• Is Part Of: ECS transactions. Volume 69:Number 10(2015)
• Page Start: 281
• Page End: 289
• Publication Date: 2015-09-14
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/06910.0281ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : The impact of the implementation of a high-k/metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number fluctuations, irrespective of the details of the gate stack. However, the trap density in the 5 nm SiO2 gate oxide, derived from the noise power spectral density is significantly increased by the application of the HKMG and/or Al2 O3 cap and the subsequent diffusion anneal at 900 o C.