Effect of CoSi2 Formation Process on CMOS Transistor Electrical Properties for Sub-100-nm Memory Applications. (1st January 2016)

• Record Type: Journal Article
• Authors: Park, Jeong Hoon; Kim, Sang Jin; Lee, Jeong Ho; Yoo, Chang Joon; Kang, Hyo Jin; Lee, Byung Cheol; Jeong, Jae Goan
• Is Part Of: ECS journal of solid state science and technology. Volume 5:Number 5(2016)
• Page Start: P264
• Page End: P271
• Publication Date: 2016-01-01
• Subjects: agglomeration -- CMOS -- CoSi2 -- dopant -- junction leakage -- metal contact; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0181605jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : We investigated the effect of various processing conditions on abnormal CoSi2 formation, such as the well-known Co spike and crystal agglomeration. We used Co metal sputtering and subsequent thermal treatment such as rapid thermal processing. The effect of the ion implantation conditions and Co deposition method were studied. To evaluate the electrical failure of transistors, we checked the chip level leakage current ( I pp ), and the unit level leakage current (JLC) in the test pattern, simultaneously. As the dopant species and concentration were believed to affect the electrical properties of every single transistor, chip level leakage current and unit level leakage current deteriorate or improve simultaneously. When we used a Ti/TiN capping layer and high-temperature physical vapor deposition, abnormal growth was suppressed and the interface became smooth. The chip level leakage current in both cases showed significant improvement; however, the unit level leakage current showed a negligible change in contrast to the chip level one. We concluded that, despite no change in unit level leakage current, the overall level of chip level leakage current improved because of the significantly decreased number of defective sites such as Co spike.