A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A. (1st January 2019)

• Record Type: Journal Article
• Authors: Marani, R.; Perri, A. G.
• Is Part Of: ECS journal of solid state science and technology. Volume 8:Number 4(2019)
• Page Start: M45
• Page End: M52
• Publication Date: 2019-01-01
• Subjects: Electron Devices -- CNTFET -- Ternary Logic Gates -- Verilog-A; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0181904jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular we propose the design of NOR/NAND gates and of a Decoder, all in ternary logic. The main novelty is that in this paper all simulations are performed in Verilog-A, avoiding so the problems presented in SPICE. At last we show that the proposed ternary logic gates consume significantly lower power and delay time than the previous CNTFET gates implementations.