Investigation of the Low Temperature / High Temperature Approach to Produce Si0.5Ge0.5 and Pure Ge Strain Relaxed Buffers. (18th August 2016)

• Record Type: Journal Article
• Authors: Hartmann, Jean-Michel; Aubin, Joris; Bogumilowicz, Yann; Delaye, Vincent; Papon, Anne-Marie
• Is Part Of: ECS transactions. Volume 75:Number 8(2016)
• Page Start: 579
• Page End: 588
• Publication Date: 2016-08-18
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07508.0579ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We have checked whether or not the Low Temperature / High Temperature approach used for pure Ge growth on Si yielded high quality Si0.5 Ge0.5 Strain-Relaxed Buffers (SRBs) that could serve afterwards as templates for thick Ge layers. We had, as soon as the Si0.48 Ge0.52 layers grown at 550°C plastically relaxed, a surface roughening which was not recovered by the 850°C growth of Si0.5 Ge0.5 (rms roughness: 5 nm). Thickening it with Ge at 750°C and using a Thermal Cycling yielded a slight surface roughness decrease, however (down to 4 nm). The HT Si0.5 Ge0.5 and pure Ge layers were slightly tensile strained. This was due to thermal expansion coefficient differences between Si and SiGe (Ge) coming into play during the cooling-down to room temperature. We had otherwise used the Ayers' theory in order to transform the full widths at half maximum of SiGe and Ge X-Ray Diffraction omega scans into Threading Dislocations Densities. We would then have, for 60° misfit dislocations in our stacks, the following values: 3.5x10 8 cm -2 in annealed 1.7 µm thick Si0.5 Ge0.5 SRBs and 1.6x10 8 cm -2 in the 1.3 µm thick Ge layers on top. Those values were definitely higher than those in 1.4 µm thick, cyclically annealed pure Ge layers grown directly on Si and in the top part of ~ 6 µm thick Si0.5 Ge0.5 linearly graded virtual substrates.