Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond. (1st January 2015)

• Record Type: Journal Article
• Authors: Gao, Shan; Smith, Ryan Scott; Cho, Jae Kyu; Choi, Seungman; Kannan, Sukeshwar; Chua, Engchye; Geisler, Holm; Kuechenmeister, Frank
• Is Part Of: ECS journal of solid state science and technology. Volume 4:Number 1(2015)
• Page Start: N3134
• Page End: N3139
• Publication Date: 2015-01-01
• Subjects: Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0221501jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.