A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. (August 2022)

• Record Type: Journal Article
• Authors: Xiao, Kanglin; Cui, Xiaoxin; Qiao, Xin; Wang, Xin'an; Wang, Yuan
• Is Part Of: Microelectronics journal. Volume 126(2022)
• Publication Date: 2022-08
• Subjects: SRAM -- Computing-in-memory (CIM) -- Digital-to-Analog-Converter(DAC)-Less -- In-memory multi-bit weight accumulation (IMMBWA) -- Prioritized subranging ADC (PS-ADC); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105506
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this work, we present a 6T SRAM computing-in-memory(CIM) macro in robust charge domain using (1) a local process element with digital-to-analog-converter-less input for eliminating non-linear and variation caused by multi-bit input, supporting XNOR and AND operations, (2) an in-memory 4-bit weight accumulation scheme for multiply-and-accumulate (MAC) operation, to reduce energy cost and achieve area-compact design, (3) a reconfigurable prioritized subranging analog-to-digital-converter for energy saving, supporting a 4-b or 4 2.24-b quantizations for multi-mode operations. The proposed design support AND and XNOR MAC operations. With a layout implementation in 28 nm CMOS process, the 128 kb SRAM CIM macro achieves good computing linearity and variation. The array area efficiency is 76.63%. The average energy efficiency is 175.2 TOPS/W while performing AND mode MAC with 2-b input and 4-b weight, and is 1379.4 TOPS/W in XNOR mode MAC. The behavioral simulation shows a classification accuracy of 85.55% in CIFAR-10. The average accuracy loss is only 1.37% compared with the software baseline.