A 16‐bit, ±10‐V Input Range SAR ADC with a 5‐V Supply Voltage and Mixed‐Signal Nonlinearity Calibration. Issue 4 (1st July 2022)

• Record Type: Journal Article
• Authors: LUO, Hongrui; ZHAO, Xianlong; JIAO, Zihao; ZHANG, Jie; WANG, Xiaofei; ZHANG, Ruizhi; ZHANG, Hong
• Is Part Of: Chinese journal of electronics. Volume 31:Issue 4(2022)
• Page Start: 690
• Page End: 697
• Publication Date: 2022-07-01
• Subjects: Wide input range -- Resistive scaling front‐end -- Mixed‐signal nonlinearity calibration -- Precision -- Successive approximation register (SAR) -- Current compensation circuit; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2021.00.057
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : This paper presents a high‐precision, successive approximation register (SAR) analog‐to‐digital converter (ADC) with resistive analog front‐end for low‐voltage and wide input range applications. To suppress the serious nonlinearity brought by the voltage coefficients of analog front‐end without deteriorating differential nonlinearity performance, a mixed‐signal calibration scheme based on piecewise‐linear method with calibration digital‐to‐analog converter is proposed. A compensation current is designed to sink or source from the reference to keep it independent of input signal, which greatly improves the linearity performance. Fabricated in a 0.5‐μ m CMOS process, the proposed ADC achieves 88‐dB signal‐to‐noise‐and‐distortion ratio and 103‐dB spurious free dynamic range with 5‐V supply voltage and 2.5‐V reference voltage, and the total power consumption is 37.5 mW.