A Low-Waste Reliable Adiabatic Platform. (January 2021) - Narimani, Reza
Abstract: Given the importance of reducing energy consumption and the challenge of heat generation in classic CMOS circuits, adiabatic circuits are believed as an appropriate alternative. Most of the adiabatic circuit families come with a dual-rail structure, which provides them with an inherent hardware redundancy. Although this redundancy could be used for improving their reliability, no studies have been previously conducted to exploit this feature. In this regard, in this paper, we show that by exploiting the inherent hardware redundancy in adiabatic circuits, their reliability could be improved, while imposing a relatively low amount of energy overhead. Subsequently, with utilizing the outcome observations, we have proposed LWRAP, a fault tolerant circuit design for dual-rail adiabatic families. While improving the reliability, LWRAP employs the well-known dynamic frequency scaling approach for mitigating the amount of imposed energy overhead in the design. Our precise SPICE simulations have shown that LWRAP improves the reliability of the circuit against transient faults by up to 12x, depending on the technology size.