A unified reconfigurable CORDIC processor for floating-point arithmetic. Issue 9 (1st September 2020)

• Record Type: Journal Article
• Authors: Fang, Linlin; Li, Bingyi; Xie, Yizhuang; Chen, He; Pang, Long
• Is Part Of: International journal of electronics. Volume 107:Issue 9(2020)
• Page Start: 1436
• Page End: 1450
• Publication Date: 2020-09-01
• Subjects: Reconfigurable architecture -- CORDIC -- Field Programmable Gate Array (FPGA) -- SAR imaging; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2020.1726497
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.