A high‐performance processor for optimal ate pairing computation over Barreto–Naehrig curves. Issue 5 (6th April 2022)

• Record Type: Journal Article
• Authors: Xie, Yujun; Wang, Bin; Zhang, Lijun; Zheng, Xin; Lin, Xiaoling; Xiong, Xiaoming; Liu, Yuan
• Is Part Of: IET circuits, devices & systems. Volume 16:Issue 5(2022)
• Page Start: 427
• Page End: 436
• Publication Date: 2022-04-06
• Subjects: Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/cds2.12116
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract: This paper presents a high‐performance processor for optimal ate pairing on Barreto–Naehrig curves over 256‐bit prime field at the 128‐bit security level. The proposed design exploits parallelism and pipeline at different levels of the pairing algorithm, including the prime field operation, the second extension of the prime field F p 2 $\left({F}_{{p}^{2}}\right)$ operation, and operations based on F p 2 ${F}_{{p}^{2}}$ . The proposed design needs 37, 271 cycles to compute optimal ate pairings. The results of implementation on a 90 nm standard cell library show that the proposed design consumes 751k gates and can compute the respective pairings in 0.10 ms. This result is at least 60 percent better than related reports in terms of normalised area‐time on ASIC. Moreover, the design is also implemented on Xilinx Virtex‐6 platform, which consumes 25K Slices and 240 DSPs and takes 0.52 ms to calculate one optimal ate pairing operation.