Scaled III–V-on-Si transistors for low-power logic and memory applications. (21st January 2021)

• Record Type: Journal Article
• Authors: Caimi, Daniele; Sousa, Marilyne; Karg, Siegfried; Zota, Cezar B.
• Is Part Of: Japanese journal of applied physics. Volume 60:Number SB(2021)
• Publication Date: 2021-01-21
• Subjects: MOSFET -- III–V -- FinFET -- DRAM -- Integration -- Logic; Physics -- Periodicals; 621.05
• DOI: 10.35848/1347-4065/abd707
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: III–V semiconductors, such as indium-rich InGaAs, are promising as replacements for the Si channel in CMOS technology. In this work, we demonstrate a scaled III–V FinFET technology, integrated on Si substrates using a direct wafer bonding technique. Logic performance down to physical gate lengths of 20 nm and fin widths of 15 nm is explored. Narrow-bandgap materials such as these are susceptible to band-to-band tunneling in the off-state, which enhances the parasitic bipolar effect (an accumulation of holes in the channel region). We here examine the use of source and drain spacers to mitigate this effect, showing a two orders of magnitude improvement in the off-state characteristics of scaled III–V FETs. The parasitic bipolar effect can also be beneficial in enabling a memory effect in the FET. In the second part of the work, we explore this effect towards capacitorless 1 T DRAM cells. We show that the use of a quantum well in these devices can enhance retention times and lead to a significant reduction of the power density.