Fabrication of vertical-taper structures for silicon photonic devices by using local-thickness-thinning process. (1st August 2022)

• Record Type: Journal Article
• Authors: Abe, Shunsuke; Hara, Hideo; Masuda, Shin; Yamada, Hirohito
• Is Part Of: Japanese journal of applied physics. Volume 61:Number SK(2022)
• Publication Date: 2022-08-01
• Subjects: silicon photonics -- vertical taper -- effective index -- integration; Physics -- Periodicals; 621.05
• DOI: 10.35848/1347-4065/ac5e4b
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: This paper describes a simple fabrication process of vertical-taper structures which can locally tune the thickness of silicon photonic devices. For low-loss spot-size conversion, taper angles less than 10° are required. To fabricate the gradual-slope shape of the vertical tapers, we have developed a step-and-exposure lithography process, which is realized by repeated light exposure to photoresist and movement of the wafer stage by using commercial steppers. The process is conducted at a lower temperature (∼120 °C) than the conventional process and is compatible with the complementary metal-oxide-semiconductor process. Also, we have made a model of the lithography to predict the angle of the taper. Theoretical angles are consistent with the experimental results. We demonstrate the conversion of a 400 nm thick silicon waveguide to 220 nm, whose length was 2.4 μ m and insertion loss was measured to be less than 0.3 dB. The process enables us to choose the optimal thickness for each silicon-photonic device.