Numerical investigation and temperature-based analysis of the analog performance of fully gate-covered junctionless FinFET. (July 2022) - Mangal, Gaurav; Tyagi, Aman; Chaujar, Rishu
Highlights: Comprehensive temperature-based short channel and analog analysis of fully gate-covered FET. The CO- and EG-JL FETs report lower degradation of characteristics at temperatures >300 K. Around ∼10 times better switching ratio and lower SS by about 20–30 mV/dec is reported at high temperatures. Analog characteristics continue with the same trend (2x better Gain, 3x better gm, and lower IOFF ). Abstract: This work presents a temperature-based investigation of the analog performance parameters of a fully gate-covered junctionless SOI FinFET, which excludes source and drain extensions. The device is studied at 20/40 nm nodes with high-k gate oxide. The design provides a higher ON-current and better short channel characteristics (<70 mV/dec SS, around 30 mV/V DIBL) with an excellent switching ratio (100x better than conventional device). The temperature investigation reveals robust device integrity at higher temperatures. The short channel parameters degrade more rapidly for the conventional device with an increase in temperature as compared to fully gate-covered devices. At 600 K, the difference of DIBL was more than 25% between the conventional and proposed devices, the SS of the device increased by about 16.67%, and the switching ratio was better by an order of magnitude. This shows that the device is a potential candidate for applications where temperature resilience is of utmost importance. Graphical abstract: Image, graphical abstract