Performance analysis of Min-Sum based LDPC decoder architecture for 5G new radio standards. (2022)

• Record Type: Journal Article
• Authors: Dinesh kumar, D.; Shantha Selvakumari, R.
• Is Part Of: Materials today. Volume 62:Part 7(2022)
• Page Start: 4965
• Page End: 4972
• Publication Date: 2022
• Subjects: LDPC -- Minimum Sum algorithm -- Error-correcting codes -- 5G NR -- FPGA; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2022.03.693
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: A low-density parity-check code (LDPC) is one of the classical error-correcting code for message transmission over noisy channel. It meets desired Shannon limit performance and is adopted as a data channel for the 5th generation new radio (5G NR) standard. This paper investigates the LDPC decoder by applying minimum-sum (MS) algorithm on the base matrix (BG1) of 5G standards. The performance of the decoder such as bit-error-rate (BER) and frame-error-rate (FER) has been improved when the number of iterations increased for larger code word. The variable node and check node architecture based on the MS algorithm with pipelining stage has been implemented in the field programmable gate array (FPGA). Based on the implementation results, it is observed that the LDPC decoder shows better performance in throughput and hardware resource usage (HUE) with some additional look-up-tables (LUT) and flip-flops (FF).