An energy efficient high-speed quantum-dot based full adder design and parity gate for nano application. (2022)

• Record Type: Journal Article
• Authors: Patidar, Mukesh; Shrivastava, Anurag; Miah, Shahajan; Kumar, Yogendra; Sivaraman, Arun Kumar
• Is Part Of: Materials today. Volume 62:Part 7(2022)
• Page Start: 4880
• Page End: 4890
• Publication Date: 2022
• Subjects: Nanoelectronics -- Quantum-dots technology -- Quantum physics -- Robust full adder -- Power dissipation -- Energy consumption; QCA Quantum-dot celular automata -- MG Majority gate -- QD Quantum-dots -- QD-E QCADesigner-E; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2022.03.532
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: Quantum-dot cellular automata (QCA) are novel prominent emerging nano-computational nanoelectronics technology at the nanoscale. It facilitated computation paradigms and promises an alternative good solution to traditional transistor CMOS technology with faster speed, very low energy dissipation, higher scale integration, small size, low latency/delay of circuits, and higher switching frequency. It is one of the most valuable nanotechnologies (or Nanotech) that effort to fabricate general computational at the nanoscopic-scale by commanding the position of electrons. In this paper, we have proposed the design of novel robust full adder, testable even and odd parity circuits using coplanar single layer in quantum-dots cellular automata nanotechnology. The proposed design of full adder circuits used only 36 quantum dots cells, occupied a design area of 0.04 µm 2, and minimum delay count is 0.75 clock cycles. The proposed circuit's investigated by novel QCADesigner-E (Energy) tool on using coherence vector (w/Energy) engine and optimized the energy-dissipation (ED) of full adder circuit. In the proposed design do not use coplanar multilayer and 45-degree rotated cells but used regular synchronized clock cycle and minimum quantum-dots cells. Therefore overall manufacturability of the robust full adder circuits significantly more improves as compared to the existing design. The presented robust full adder design have been calculated the total ED (Sum_Ebath ) is 1.70e−002 eV (Error: +/- −1.63e−003 eV), and average ED/cycle (Avg_Ebath ) is 1.54e−003 eV (Error: +/- −1.48e−004 eV).