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HARVARD Citation
Yadav, S. et al. (2022). Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs. Semiconductor science and technology. p. . [Online].
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Yadav, S. et al. (2022). Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs. Semiconductor science and technology. p. . [Online].