A 4-channel front-end electronics for muon drift tubes detectors in 65 nm CMOS technology. (1st July 2022) - Shah, S.A.A.; De Matteis, M.; Fras, M.; Kortner, O.; Kroha, H.; Richter, R.; Baschirotto, A.
Abstract: A 4-channel front-end electronics chip in 65 nm CMOS technology (ASD65 nm) for muon drift tube chambers at high background counting rates in the ATLAS detector at High-Luminosity LHC and in future high-energy collider experiments is presented. Each channel of the ASD65 nm chip is a mixed-signal processing circuit consisting of a Charge Sensitive Preamplifier (CSP), a two-stage shaper, and a timing discriminator. The CSP exhibits a peaking time of 11 ns and a sensitivity of 1.1 mV/fC. The peaking time of the full analog chain is 14.6 ns. The minimum signal-to-noise ratio of the channel is 15 dB for the minimum input charge of 5 fC, and it rises to 40.5 dB for the maximum input charge of 100 fC. At the output, the time representation of input signal is provided in both, CMOS level as well as low-voltage-differential-signal. Each channel consumes a current of 10.6 mA from a single 1.2 V supply, and occupies an area of 0.235 mm 2 . The specified performance parameters of the ASD65 nm have been achieved for 60 pF parasitic capacitance of the detector connected the input terminal.