A novel compact asymmetric Doherty PA design using symmetric transistors. Issue 9 (14th June 2022) - Jin, Liwei; Cheng, Zhiqun; Wang, Yonghui; Liu, Guohua
Abstract: A novel 7.2 dB output power back off Doherty power amplifier (DPA) based on asymmetrical load is proposed using two same transistors in this paper. To get maximum efficiency at back‐off output power and the largest saturate output power level simultaneously, the carrier power amplifier (PA) is matched to the maximum efficiency region when peaking PA is almost off, and both of the two PAs are matched to maximum power region to get largest output power. According to the proposed design methodology, high efficiency at back‐off power and high peak power DPA is designed and fabricated with two Cree's GaN HEMT CGH40010F devices. Measurements results show that the saturated output power of the DPA is over 44.5 dBm, the drain efficiency when 7.2 dB output power back off and saturate power are above 42% and 53%, respectively, in the range of 3.4–3.8 GHz. Meanwhile, better than −47.8 dBc adjacent channel leak power ratio can be achieved with digital predistortion under 20 MHz LTE signal testing at 3.4 GHz, the final design size is only 14 × 12 cm 2 .