New digital background calibration method for pipelined ADCs. Issue 4 (3rd June 2020)

• Record Type: Journal Article
• Authors: Zia, Ehsan; Farshidi, Ebrahim; Kosarian, Abdolnabi
• Is Part Of: Compel. Volume 39:Issue 4(2020)
• Page Start: 871
• Page End: 884
• Publication Date: 2020-06-03
• Subjects: Electric converters -- Circuit analysis -- Background -- Calibration -- FPGA -- Initialization -- Newton – Raphson -- Pipelined ADC; Electrical engineering -- Data Processing -- Periodicals; Electrical engineering -- Mathematics -- Periodicals; Electrical engineering -- Periodicals; Electronics -- Data Processing -- Periodicals; Electronics -- Mathematics -- Periodicals; 621.3
• DOI: 10.1108/COMPEL-10-2019-0396
• Languages: English
• ISSNs: 0332-1649

Abstract

Abstract : Purpose: Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach: The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings: Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2, 000 clock cycles. Practical implications: The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value: The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.