A novel approach for designing of variability aware low‐power logic gates. Issue 3 (3rd March 2022)

• Record Type: Journal Article
• Authors: Sharma, Vijay Kumar
• Is Part Of: ETRI journal. Volume 44:Issue 3(2022)
• Page Start: 491
• Page End: 503
• Publication Date: 2022-03-03
• Subjects: CMOS -- ICS -- Monte Carlo simulation -- nanoscale regime -- ultra‐low power -- VLSI; Telecommunication -- Periodicals; Electronics -- Periodicals; Electronics; Telecommunication; Periodicals; Periodicals; 621.38205
• DOI: 10.4218/etrij.2020-0213
• Languages: English
• ISSNs: 1225-6463

Abstract

Abstract: Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters.