Design and implementation of ternary adder for High-Performance arithmetic applications by using CNTFET material. (2022)

• Record Type: Journal Article
• Authors: Panwar, Uday; Sharma, Parul
• Is Part Of: Materials today. Volume 63:(2022)
• Page Start: 773
• Page End: 777
• Publication Date: 2022
• Subjects: - CNTFET -- Ternary Logic -- Low Power -- GDI; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2022.05.316
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: This work presents 1-bit hybrid full adder cell using proposed ternary logic along with carbon nanotube. The novelty of this design is the remarkable optimization of power consumption by reducing the hardware part which makes it area efficient and low power. Wide bandwidth and High speed are other salient features of the presented design. To begin with Proposed ternary logic, it works in three logic level in addition to that it improvises dynamic performance of full adder along with CNT technology to maintain the law of scalability for enhancing the silicon technology. The work has been simulated on HSPICE software using 32 nm process CNTFET technology. The operation voltage was.9V at 100 MHz frequency. The relative improved percentage in the area and PDP to be found 13.01–56.18% and 14.27–58.54% respectively. In order to provide fair comparison relative data of similar studies and simulated results has been carried out and put in the tabular form in the later part of the paper.