3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications. Issue 2 (4th March 2022)

• Record Type: Journal Article
• Authors: Baidya, Achinta; Lenka, Trupti R.; Baishya, Srimanta
• Is Part Of: IETE journal of research. Volume 68:Issue 2(2022)
• Page Start: 1342
• Page End: 1349
• Publication Date: 2022-03-04
• Subjects: High-k dielectrics -- Junctionless transistor -- Logic gates -- Mixed-mode simulation -- Pass transistor logic; Electronics -- Periodicals; Telecommunication -- Periodicals; Electronics; Telecommunication; Periodicals; 621.38
• DOI: 10.1080/03772063.2019.1649203
• Languages: English
• ISSNs: 0377-2063

Abstract

Abstract : We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic logic gates: AND, OR, XOR are designed using only the n-type junctionless nanowire transistor with HfO2 gate dielectric. Simulations of these circuits have been studied and analyzed under a mixed-mode environment. Outcomes of the analysis show that 3D dual gate junctionless nanowire transistor with 20 nm gate length well performed for pass transistor logic. In addition, a junctionless nanowire transistor-made multiplexer has also been studied and found to perform well. A high-k gate dielectric was used for all junctionless transistors as the higher k value improves the device characteristics and circuit performances. Our study also shows that the junctionless nanowire transistor-based pass transistor logics for digital circuit perform well.