A low-noise and fast transient response LDO design for high-speed SerDes. Issue 1 (1st February 2022)

• Record Type: Journal Article
• Authors: Song, Shengyu; Chen, Jianjun; Yuan, Hengzhou; Xing, Haiyuan; Wen, Yi
• Is Part Of: Journal of physics. Volume 2187:Issue 1(2022)
• Publication Date: 2022-02-01
• Subjects: Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/2187/1/012006
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: In order to deal with the special needs of high-speed digital-analog hybrid circuits for power supplies, this article has designed a LDO circuit specifically applied to high-speed SerDes. In the design process, a cross-coupled charge pump was used to increase the swing and reduce power supply noise, and to increase the gain and reduce the area overhead, the design of an asymmetric operational amplifier was introduced. At the same time, the use of the cascode structure is also conducive to the frequency stability of the loop and provides sufficient phase margin for the circuit. Through simulation verification, the low-frequency maximum internal noise of this LDO is only 0.96uV/sqrt(Hz), the transient response time when the load changes from low to high is 38ns, the transient response time from high to low is 84ns, the phase margin is 87.3deg, and the PSRR is 56.8dB.