Reduce Wafer Remnants Through Pre-Assembly Process Optimization. Issue 1 (1st January 2022)

• Record Type: Journal Article
• Authors: Vijayakumaran, P.; Ramli, M. H. M.; Selvam, M.; Hamid, K.; Atiqah, A.; Jalar, A.; Bakar, M. A.
• Is Part Of: Journal of physics. Volume 2169:Issue 1(2022)
• Publication Date: 2022-01-01
• Subjects: Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/2169/1/012001
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: Wafer fabrication technology has been seeing exponential growth in recent years. This development is driven by the demand for better reliability, superior performance, and lower cost of electronic consumer products. Generally, the standard soft-soldering wafer backside metallization multilayer stack is AuAs/Ag/Ni/Ag. The present backside metallization being developed is Ti/NiV/Ag as the cost of Ti is almost neglectable compared to Au. However, this new wafer backside metallization leads to increased remnants remaining on the dicing tape after die pickup. The reduced effective area of the die backside surface may cause adhesion issues in the subsequent die attach process. In realizing this essential phase, in pre-assembly process optimization has been carried out using some assessment on the process flow and data analysis through statistical analyses image and measurement of wafer skeleton remnants was taken showing a reduction from 70μm to 40μm in width. This method shows that skipping the baking process in the pre-assembly process will undoubtedly lessen the adhesion with the back metal with mounting tape. Without compromising the saw quality will indeed give a reduced wafer remnant. Henceforth, skipping baking in the pre-assembly process will significantly reduce wafer remnants and further improve die attach process.