An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection. (February 2021) - Sahoo, Jagamohan; Mahapatra, Rajat; Bhattacharayya, Amalendu Bhusan
Abstract: A simulation study of the Off-State breakdown characteristics for a dual-dummy-gate SOI-LDMOS transistor is presented. The proposed device is a modification of a bulk-LDMOS transistor with a single dummy gate and two different diffused layers in the drift region. It introduces two additional dummy gates in the drift region, apart from the gate and extended drain electrode in the conventional device. The dummy gates need to be optimally biased to maximise the breakdown ( V BR ) and snapback voltages. 1D model modifying the 2D Poisson's equation has been proposed to analyse the 2D phenomena arising due to the perpendicular electric field originating from the dummy gate and extended-drain voltages and optimize the two dummy-gates bias. This approach provides an analytical solution for the Off-State V BR under the depletion condition. The model is verified with the TCAD simulations. The simulation results provide an insight into the electric field, potential distributions, and carrier concentrations in the drift region that characterizes the device performance. The impact ionization and current density contours are also included. It is found that the introduction of the two dummy gates enhances the maximum achievable V BR while it eliminates the need to have two different diffused regions that necessitate additional masks. Also, the proposed device has an intrinsic structural advantage of the reduced gate to drain capacitance due to the shielding effect of dummy gates. As the performance of the proposed device is controlled externally by the applied dummy gate voltage, the V BR is user programmable as per the requirement in electrostatic discharge (ESD) protection circuits for a sub-100 V application. Highlights: A new Dual-Dummy-Gate SOI-LDMOS transistor, where the breakdown voltage is programmed electronically. A one-dimensional model modifying the 2D Poisson equation under the dummy gate has been proposed for the optimization of the two-dummy gate bias under the required depletion condition. The model is verified with the results obtained from TCAD (ATLAS) simulations. Enhancement of the breakdown voltage has been reported as compared to the single dummy gate SOI-LDMOS and the conventional SOI-LDMOS transistor.