Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC. (1st April 2022)

• Record Type: Journal Article
• Authors: Hung, Chia-Lung; Tsui, Bing-Yue; Tsai, Te-Kai; Lin, Li-Jung; Wen, Yu-Xin
• Is Part Of: ECS journal of solid state science and technology. Volume 11:Number 4(2022)
• Publication Date: 2022-04-01
• Subjects: SiC -- complementary metal–oxide–semiconductor (CMOS) -- integrated circuit (IC) -- local oxidation of SiC (LOCOSiC) isolation -- compromised gate dielectric -- static random-access memory (SRAM); Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2162-8777/ac6119
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : In this study, the performance of complementary metal–oxide–semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth ) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vth were characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.