Top-down design methodology for a 2 ps rms Jitter at 2.56 GHz of an analog PLL based on Ring and LC Tank Oscillators. (1st May 2022) - Bechetoille, E.; Joly, B.; Lemaire, O.; Laktineh, I.; Manen, S.; Mathez, H.; Russo, P.; Vallerand, P.; Vandaele, R.
Abstract: A top-down methodology is proposed to design Phase-Locked-Loops (PLL) using behavioural and transistor-level simulation in two cases: Ring-Oscillator (RO) and LC Tank Oscillator (LCTO) with the aim to achieve a low-jitter PLL clock generator in 130 nm process. The optimization of these two PLLs is obtained in three steps. The first one is to design a model in Verilog-A of each block with its intrinsic jitter parameter. Each block is simulated alone to verify the nature of its intrinsic jitter: Frequency Modulation jitter (FM jitter) or Phase Modulation jitter (PM jitter). The second step is to place each of these blocks in a global schematic to obtain a full behavioural PLL. In this way, one can study the PLL operation and check the effect of each block's jitter on the PLL output. The third step is to use the intrinsic FM jitter or PM jitter values to simulate at the transistor level of each block individually and then all of them together. To evaluate the loop bandwidth and the loop stability of each of the two PLLs, a linearized PLL is designed using ideal sources. This approach is important to check the compatibility of each block in terms of jitter and bandwidth with respect to the target PLL performance. The optimization results are used to design and produce two PLLs. Measurements of these two are found to have an absolute time jitter of the order of 2 ps rms.