Design of a 9-bit column-parallel ADC in the MAPS for real-time beam monitoring. (1st January 2022) - Cao, B.; Wang, Y.; Wen, Y.; Tian, Y.; Liao, J.; Lu, W.; Wang, H.; Yang, H.; Li, X.; Niu, X.; Zhou, W.; Zhao, C.
Abstract: This paper describes a 2 Msps 9-bit column-parallel ADC for monolithic active pixel sensor. It is designed in fully differential cyclic architecture and takes eight clock cycles to perform a 9-bit conversion. This ADC is fabricated in a 130 nm CMOS process. Each ADC covers a small area of 100 µm × 300 µm and consumes ∼5 mW. The measurement results show that this ADC has a signal-to-noise and distortion ratio (SNDR) of 46.8 dB. The DNL (Differential Nonlinearity) and (Integral Nonlinearity) INL are 0.168 LSB and 0.112 LSB, respectively. The effective number of bits (ENOB) is 7.48 bits.