A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications. (1st January 2022) - Meng, C.; Guo, T.; Xiong, T.; Chen, Q.; Guo, Z.; Zhao, C.; Guo, D.
Abstract: This paper presents the design and the test results of a low-power 5 Gbps 10:1 serializer chip with the self-check function based on a standard 130 nm CMOS technology. This serializer chip adopts a multi-level design scheme with a combination of the multi-phase structure (5:1 module) in the low data rate part and the tree structure (2:1 module) in the high date rate part. The high data rate 2:1 module adopts a latch-induced latency control circuit to ensure the timing margin across corners. The serializer chip has been fully tested, wide-open 5 Gbps output eye diagram has been captured, and the logic function has also been verified. The measured power consumption of the whole chip is 42 mW including Rx/Tx, and the power consumption of the serializer core is around 12.1 mW.