Onchip digital calibrated 2 mW 12-bit 25 MS/s SAR ADC with reduced input capacitance. (1st April 2022) - Hernandez Herrera, H.D.; Bregant, M.; Sanchez, B.; Van Noije, W.
Abstract: We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2 pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 2 fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to digitally compensate for the mismatch non-linearity directly over the ADC output. The circuit consumes 2 mW at 25 MS/s on a core area of 300 μm × 500 μm in 180 nm CMOS technology. ENOB improvements of 0.85 bits were post-layout simulated after calibration. Sample characterization is ongoing.