130‐nm BiCMOS design of low‐pass negative group delay integrated RL‐circuit. (7th March 2022) - Ravelo, Blaise; Rahajandraibe, Wenceslas; Guerin, Mathieu; Agnus, Benoît; Thakur, Preeti; Thakur, Atul
Abstract: A design method of low‐pass (LP) negative group delay (NGD) integrated circuit (IC) implemented in 130‐nm BiCMOS technology is investigated. The LP‐NGD circuit is composed by RL‐network with BiCMOS high Ohmic unsalicided N+poly resistor and symmetrical high current spiral inductor. The design methodology of the investigated LP‐NGD circuit is explained by chip layout process. Then, the pre‐simulation is performed with the design rule check (DRC) and 225 μm × 215 μm layout versus schematic (LVS) approaches. The LP‐NGD design feasibility of the BiCMOS IC implementation is validated by AC frequency domain simulation with realistic component implementation constraints. As expected, the ideally calculated and simulated results show NGD of about −100 ps with 1.12 GHz cut‐off frequency and −6 dB attenuation. Moreover, the LP‐NGD function is also verified with transient analyses with Gaussian pulse and arbitrary waveform signals. As expected, despite the attenuation, the output signal leading and tailing edges appear in time‐advance of about −100 ps compared to the input ones. Abstract : This paper presents an innovative 130‐nm BiCMOS design of LP‐NGD integrated circuit (IC). The analysis and synthesis method of RL‐network based IC is developed. The effectiveness of the method is validated by CADENCE VIRTUOSO simulation in both frequency and time domain.