High-resistivity silicon-based substrate using buried PN junctions towards RFSOI applications. (August 2022) - Moulin, M.; Rack, M.; Fache, T.; Chalupa, Z.; Plantier, C.; Morand, Y.; Lacord, J.; Allibert, F.; Gaillard, F.; Lugo, J.; Hutin, L.; Raskin, J.P.
Highlights: This paper shows the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (ρeff) figure of merit of a High-Resistivity (HR) substrate suffering from Parasitic Surface Conduction layer (PSC). We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2 kΩ.cm with 0.1 dB/mm loss at 6 GHz for a HR + PN substrate. Temperature, dose and implantation energy variations were performed in order to identify the buried PN junctions robustness. At high-temperature, HR + PN substrate still shows an enhancement of RF performance. Abstract: In this paper, we aimed to show the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (ρeff ) figure of merit of a High-Resistivity (HR) substrate suffering from Parasitic Surface Conduction layer (PSC). We characterize Coplanar Waveguides (CPW) in order to monitor the substrate frequency response. We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2 kΩ.cm with 0.1 dB/mm loss at 6 GHz for a HR + PN substrate. PN pattern, temperature and implantation conditions varations were performed in order to identify the buried PN junctions robustness. At high-temperature, HR + PN substrate still shows an enhancement of RF performance. Contrary to HR w/o PN, HR + PN is bias independent. This method is suitable for local PSC passivation, targeting advanced SoC (System-on-Chip) in FD-SOI technology for next wireless communication generations and embedded RF electronics.