Fully integrated switched‐inductor switched‐capacitor dual‐path DC–DC converter. (14th February 2022)

• Record Type: Journal Article
• Authors: Meshkat, Amin; Dehghani, Rasoul; Farzanehfard, Hosein
• Is Part Of: International journal of circuit theory and applications. Volume 50:Number 6(2022)
• Page Start: 2035
• Page End: 2054
• Publication Date: 2022-02-14
• Subjects: cascode buck converter -- fully integrated voltage regulator -- high current density -- high step‐down -- inductor quality factor boosting -- on‐chip inductor optimum design; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3245
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A fully integrated switched‐inductor switched‐capacitor (SISC) DC–DC converter is proposed. This converter is designed in such a way that the input voltage can be twice the process allowable voltage without damaging the on‐chip transistors. To mitigate large series resistance of on‐chip inductors as one of the main challenges in the switched‐inductor power supply on chip, two solutions are proposed. By using analytical model of an on‐chip inductor, optimal physical dimensions are designed to achieve the desired inductance with minimum series resistance in a small area. Along with the optimization, the dual‐path structure of the proposed converter reduces series resistance losses of the on‐chip inductor and increases the effective quality factor up to 7 times in duty cycle of 0.8. The proposed converter is implemented in 0.18 μm standard CMOS process. The circuit converts input voltage of 3.6–0.9 V at the load current of 125 mA with the efficiency of 72.8%. Efficiency enhancement factor reaches 72% at 600 mV output voltage. The achieved current density of the proposed converter is 333 mA/mm 2 . By calculating small signal model of the proposed converter and designing a suitable feedback loop, an appropriate transient behavior was proved Abstract : In this work, a method is presented to implement a fully integrated dc–dc converter. Input dc voltage higher than the maximum permissible voltage of the used technology is down‐converted with high efficiency. This is because of using an optimized on‐chip inductor and providing two parallel switched‐capacitor and switched‐inductor paths to supply the output power. This feature reduces the current flowing through the output series inductor and causes significant improvement of the inverter efficiency.