A delay cell with duty-cycle correction and parasitic compensation for large array indirect time-of-flight CMOS image sensors. (July 2022)

• Record Type: Journal Article
• Authors: Wang, Zeqing; Li, Qiang; Nie, Kaiming; Xu, Jiangtao; Tian, Guan; Gao, Jing
• Is Part Of: Microelectronics journal. Volume 125(2022)
• Publication Date: 2022-07
• Subjects: Time-of-flight (ToF) -- CMOS image sensor -- Duty cycle correction (DCC) -- Parasitic compensation (PC) -- Phase interpolator -- DLL; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105448
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Large array indirect time-of-flight (ToF) CMOS image sensors use a self-compensating voltage-controlled delay line (VCDL) to decrease the peak current of the demodulation circuit. However, the ToF detection error is affected by the output duty cycle of the self-compensation VCDL. This paper analyzes the relationship between the output duty cycle of the self-compensation VCDL and the ToF detection error. A delay cell with duty cycle correction and parasitic compensation is proposed. A phase interpolator is also used to improve the output phase resolution of the self-compensating VCDL. This design is implemented using the 0 . 11 μ m CMOS process. The post-simulation results show that the correction range of this design is 0.9% to 98% at 100 MHz. By applying the proposed delay cell to the self-compensating VCDL, the delay of one delay cell is reduced by 163 ps due to the parasitic compensation circuit. Moreover, the ToF detection error decreases by 2.03 cm compared to the traditional structure.