Parametric investigation and trap sensitivity of n-p-n double gate TFETs. (May 2022) - Deb, Deepjyoti; Goswami, Rupam; Baruah, Ratul Kr; Kandpal, Kavindra; Saha, Rajesh
Highlights: Gate-on-drain length in npn TFET is similar to gate-drain underlap in pin TFET. Trap sensitivity peak positions shift when gate length lies within the BTBT region. BTBT and TAT rates compete among themselves to affect the transfer characteristics. Abstract: This article reports an architecture of a silicon-on-insulator (SOI) tunnel field effect transistor (TFET) possessing an n-p-n body, where the two p-n junctions serve as the primary tunneling sites. The p -type source region is elevated allowing two gate structures to modulate the bands over the two junctions, thus forming a double gate structure. The architecture is optimized in terms of doping concentration, and geometrical dimensions defined in analogy with the conventional geometry of TFET through calibrated simulations using industrial technology computer aided design (TCAD) tool. The article further incorporates three gate engineering techniques to the n-p-n architecture to improve the electrical performance. The trap sensitivity of the architectures is reported for concentration, and energy positions of acceptor-like and donor-like traps at the semiconductor-oxide interface. Additionally, the impact of trap-assisted tunneling on the device characteristics is examined. Graphical Abstract: Image, graphical abstract