Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters. (July 2022) - Kumari, N. Aruna; Prithvi, P.
Abstract: In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For each nanosheet, the thickness (NT ) varied from 5 nm to 9 nm and width (NW ) varied from 10 nm to 50 nm to analyze the performance variations with the device's geometry. It is observed that DC metrics like switching ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS) degrade with increment in geometry of NS. Moreover, the increment in analog/RF FOMs like transconductance (gm ), output conductance (gds ), cutoff frequency (fT ), transconductance frequency product (TFP), and gain bandwidth product (GBW) is observed as the width and thickness are increase towards 50 nm and 9 nm, respectively. However, intrinsic gain, GFP, and GTFP deteriorate as the physical dimensions of the NSFET increase. On top of that, inverter and ring oscillator (RO) circuits are designed and the performance is demonstrated by varying width of the nanosheet. The circuit analysis is performed in Cadence Virtuoso tool by using look-up table based Verilog-A model. A decrement of 17.6% in the delay of the inverter is noticed when the width is increased from 10 nm to 50 nm. Also, it is observed that the static current of inverter is less than pA, which ensures less static power dissipation. Furthermore, an increment of 46.5% in f osc of 3-stage RO is observed as width increased to 50 nm. According to the various results analyses, NSFET is a promising device for high performance and high frequency analog/RF applications for sub-7-nm technology nodes.