Timing analysis algorithm using a neural network under PVT variations. (July 2022) - Liu, Yan; Ma, Yan-Hua; Chang, Yu-Chun
Abstract: Process-voltage-temperature variations result in an increase in logic gate delays, which further lead to timing violations. Because of the computational complexity of the operators such as max and sum in statistical static timing analysis, this paper proposes a timing analysis algorithm using neural network to evaluate circuit timing under the PVT variations. In the proposed algorithm, a neural network method is applied to model the mean or standard deviation of the gate delay. Then, a viability analysis method is introduced to recognize the true critical path. The simulation results on ISCAS89 benchmarks illustrate that compared with SPICE Monte Carlo simulation, the error in the mean calculated by the proposed algorithm is less than 2%, and the error in the standard deviation is less than 3.64%. In addition, for s298, s344, s832, s1238 and s13207, the viability analysis algorithm achieves 1.04X, 1.01X, 2.77X, 1.62X and 4.48X speedup over full path search, respectively.