A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate. (March 2018)

• Record Type: Journal Article
• Authors: Nayak, Debasish; Acharya, Debiprasad Priyabrata; Rout, Prakash Kumar; Nanda, Umakanta
• Is Part Of: Microelectronics journal. Volume 73(2018)
• Page Start: 43
• Page End: 51
• Publication Date: 2018-03
• Subjects: Bit-interleaving -- Half-selected disturbance -- Stability -- Leakage current -- Process variation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.01.008
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The impact of alpha particle and exposure to cosmic radiation has multifold the existing stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the half selected cell of a SRAM array is another serious issue which degrades the stability of a cell as well as waste energy through the half selected cells. The proposed highly stable 8T-SRAM cell takes care of both the above mentioned issues effectively. The cell is capable to be arranged in a bit-interleaving fashion which can then use a conventional error correction code (ECC) to correct the single bit error caused by the exposer to cosmic radiation. Traditionally the read stability and write ability are conflicting to each other and any one of them can be enhanced with sacrificing the other. But the proposed cell enhances both the read stability and the write ability simultaneously. Two other cells namely the 8T differential (8T-DIFF) SRAM and 9T read disturbance free (9T-RDF) SRAM are compared with the proposed SRAM cell which consume 20.1% and 16.2% more energy respectively. The read speed of the proposed SRAM is significantly higher than the 9T-RDF SRAM and marginally higher than the 8T-DIFF SRAM. The write speed of the proposed SRAM is also better than the two compared SRAM.