A 600 mV +20 dBm IIP3 CMOS LNA with gm smoothening auxiliary path for 2.4 GHz wireless applications. (18th July 2022)

• Record Type: Journal Article
• Authors: Rao, D. Sharath Babu; Sumalatha, V.
• Is Part Of: International journal of innovative computing and applications. Volume 13:Number 3(2022)
• Page Start: 127
• Page End: 137
• Publication Date: 2022-07-18
• Subjects: 80211 b/g/n -- wireless LAN -- wireless sensor networks -- WSN -- wireless personal area networks -- WPAN -- low noise amplifier -- LNA -- BSIMv3 -- cascode LNA -- folded cascode LNA -- MDS technique; Evolutionary computation -- Periodicals; Neural networks (Computer science) -- Periodicals; Genetic programming (Computer science) -- Periodicals; Biologically-inspired computing -- Periodicals; Swarm intelligence -- Periodicals; Quantum computers -- Periodicals; 006.3
• Languages: English
• ISSNs: 1751-648X

Abstract

CMOS low noise amplifiers (LNA's) finds a large-scale of applications in biomedical applications and other mission sensors which include cordless telephones, wireless keyboards, and radio equipment. For radio-frequency (RF) applications where signal frequencies are high, consequences of intermodulation distortion results from the nonlinearities of the MOS transistors used in the LNA. As it is impracticable to eradicate nonlinearities completely, second-order nonlinearities were added in out of phase with the third-order nonlinearities in derivative and modified derivative methods which suppress the third-order nonlinearities up to an input intercept point (IIP3) of 8 dBm only. In this article, proposed LNA reduces the nonlinearity interaction increases the IIP3 performance up to 12 dBm using the common source differential architecture with PMOS loads in the auxiliary path. The proposed LNA offers gain (S21) of 12 dB operates at ultra-low voltage supply headroom of 600 mV with good stability deemed as a favourable requirement for low power wireless applications.