Implementation of TRNG with SHA-3 for hardware security. (May 2022)

• Record Type: Journal Article
• Authors: Kamadi, Annapurna; Abbas, Zia
• Is Part Of: Microelectronics journal. Volume 123(2022)
• Publication Date: 2022-05
• Subjects: RNG -- TRNG -- PRNG -- HRNG -- MLFSR -- Sponge function -- Hash algorithm -- Keccak -- Cryptography -- ILA -- FPGA Zed board -- NIST -- Diehard; RNG Random Number Generator -- TRNG True Random Number Generator -- PRNG Pseudo Random Number Generator -- HRNG Hardware Random Number Generator -- LFSR Linear Feedback Shift Register -- RO Ring Oscillator -- FPGA Field Programmable Gate Array -- ILA Integrated Logic Analyzer -- JTAG Joint Test Action Group -- IP Intellectual Property -- NIST National Institute of Standards and Technology -- MD Message Digest -- SHA Secure Hash Algorithm -- RTL Register Transfer Level -- HDL Hardware Description Language -- LUT Look Up Table -- FF Flip-Flop -- Mbps Mega bits per second -- Gbps Giga bits per second -- ns Nano second -- FIPS Federal Information Processing Standard -- XOR The Boolean Exclusive-OR operation -- MHz Mega hertz -- IOT Internet Of Things -- XDC Xilinx Design Constraints; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105410
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Random Number Generators (RNGs) are the solution for cryptographic applications to enhance hardware security. These RNGs ought to have three specific properties unpredictability, aperiodic, and good statistical criteria. This brief presents a True Random Number Generator (TRNG) based on Ring oscillators' jitter with MLFSR. The MLFSR is augmented with a set of prime primitive polynomials, Boolean, and non-linear functions to attain a non-linear, unpredictable, and extended sequence period. Paper mainly focused on achieving high randomness by integrated the TRNG with a new promising crypto engine Keccak as a post-processing block; leads to extensively more security in data transfer, encryption keys, data authenticity of ICs, and IoT based applications. The RNG design is coded in Verilog HDL and implemented on the FPGA Zed board. Hashing is performed with a throughput of 2.4Gbps at 100 MHz either with RNG data or SHA data. Evaluated the randomness of the generated non-deterministic bitstreams (10 Mb) using the NIST 800–22 & Diehard test suite and successfully passed.