Unsupervised novelty pattern classification of shmoo plots for visualizing the test results of integrated circuits. (15th September 2022) - Shin, Hyun Soo; Kim, Youngju; Kim, Chang Ouk; Park, Sung Ho
Highlights: Shmoo plots in semiconductor manufacturing are used for indicating device state. We address high-dimensional and multiclass imbalance challenges for shmoo plots. We introduce a feature extraction process for presenting clear shmoo plot patterns. We propose a two-stage clustering process to solve multiclass imbalance situations. To demonstrate the applicability of the proposed model, real field data is used. Abstract: Shmoo plots are visual tools for verifying the performance of integrated circuit devices, where each cell in a plot records whether the examined device operates normally under the test condition. When identifying the device state, the overall pass/fail pattern appearing in the shmoo plot is more important than the test results for individual conditions. Because similar shmoo plots indicate similar device characteristics, defect causes, and process peculiarities, engineers can analyze device quality and defect causes by classifying shmoo plot patterns. Most mass-produced devices have high and stable yields, whereas defect devices are incredibly scarce. If engineers classify numerous device plots manually at a semiconductor test site, significant time and resources will be required, and the result will likely vary based on the engineers' experience. Therefore, shmoo plot usage is limited unless an automatic classification model is adopted. Moreover, training high-performance pattern classifiers that do not overfit the models is difficult because shmoo plots contain high-dimensional data and unlabeled, multiclass imbalanced datasets, where the number of defects is smaller than that of normal plots and pattern labels are seldom assigned. In this study, we propose a novel feature extraction process and a two-stage clustering process to distinguish novel shmoo plot patterns. Actual shmoo plots obtained from a wafer test stage are used to compare the experimental results obtained via the proposed method and conventional methods, and they verify the superiority of the proposed method.