Fermi‐Level Pinning‐Free WSe2 Transistors via 2D Van der Waals Metal Contacts and Their Circuits. Issue 19 (4th April 2022)

• Record Type: Journal Article
• Authors: Jang, Jisu; Ra, Hyun‐Soo; Ahn, Jongtae; Kim, Tae Wook; Song, Seung Ho; Park, Soohyung; Taniguch, Takashi; Watanabe, Kenji; Lee, Kimoon; Hwang, Do Kyung
• Is Part Of: Advanced materials. Volume 34:Issue 19(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-04-04
• Subjects: 2D materials -- complementary metal‐oxide‐semiconductors -- Fermi‐level pinning -- Schottky–Mott limit -- van der Waals contacts; Materials -- Periodicals; Chemical vapor deposition -- Periodicals; 620.11
• DOI: 10.1002/adma.202109899
• Languages: English
• ISSNs: 0935-9648

Abstract

Abstract: Precise control over the polarity of transistors is a key necessity for the construction of complementary metal–oxide–semiconductor circuits. However, the polarity control of 2D transistors remains a challenge because of the lack of a high‐work‐function electrode that completely eliminates Fermi‐level pinning at metal–semiconductor interfaces. Here, a creation of clean van der Waals contacts is demonstrated, wherein a metallic 2D material, chlorine‐doped SnSe2 (Cl–SnSe2 ), is used as the high‐work‐function contact, providing an interface that is free of defects and Fermi‐level pinning. Such clean contacts made from Cl–SnSe2 can pose nearly ideal Schottky barrier heights, following the Schottky–Mott limit and thus permitting polarity‐controllable transistors. With the integration of Cl–SnSe2 as contacts, WSe2 transistors exhibit pronounced p‐type characteristics, which are distinctly different from those of the devices with evaporated metal contacts, where n‐type transport is observed. Finally, this ability to control the polarity enables the fabrication of functional logic gates and circuits, including inverter, NAND, and NOR. Abstract : A creation of clean van der Waals contacts is reported. Clean contacts made from 2D metal Cl–SnSe2 can completely eliminate the Femi‐level pinning, permitting ideal Schottky barrier heights and polarity‐controllable transistors. With the ability to control the carrier polarity, various functional logic gates and circuits (inverter, NAND, and NOR) are demonstrated by integrating WSe2 transistors with Cl–SnSe2 contacts.