A novel time-domain method for fault detection and classification in VSC-HVDC transmission lines. (September 2022) - Imani, Amir; Moravej, Zahra; Pazoki, Mohammad
Highlights: Proposing a fault detection and classification scheme for bipolar HVDC system without communication medium using ITD algorithm. An analytical procedure of setting the ITD's parameters is presented to determine the optimal number of iteration and threshold value index of fault identification process. More efficient performance in fault detection and classification in the case of recognition speed, simplicity, setting free, and low computation burden. The robustness of proposed protection scheme is evaluated by changing the fault parameters such as: fault resistance and fault location. The impact of noise contamination, sampling frequency and changing smoothing reactor parameters are validated, as well. The simulation validation is carried out in two benchmark models of MATAB and PSCAD software. Abstract: The short circuit fault current is one of the worst contingencies in voltage source converter (VSC)-based high voltage direct current (HVDC) system. Therefore, having a fast, robust, and selective protection scheme is necessary in HVDC systems. In this paper, a non-communication-based protection scheme is presented using Intrinsic Time Decomposition (ITD) technique in a HVDC system. This time domain approach owns some prominent features such as high speed, low sampling rate and computational burden and no need for parameter's setting. The proposed protection scheme relies on the current signal sampled from the single end. The concept is to obtain the proper rotation component (PRC) of input signal and computing an energy index named Teager Kaiser Energy Operator (TKEO) to identify the fault occurrence in a HVDC line. The performance of the proposed scheme has been assessed against various scenarios including external disturbance such as ac faults and abrupt change of active power in two standard sample systems in MATLAB/SIMULINK and PSCAD/EMTDC environments. In addition, a wide range of internal dc faults are studied to evaluate the sensitivity of the scheme. The appropriate performance of the scheme is verified and the fault detection and classification tasks are done in less than 1 ms.