An extendable asymmetric boost multi‐level inverter with self‐balanced capacitors. (1st December 2021)

• Record Type: Journal Article
• Authors: Karimi, Mahdi; Kargar, Paria; Varesi, Kazem
• Is Part Of: International journal of circuit theory and applications. Volume 50:Number 4(2022)
• Page Start: 1297
• Page End: 1316
• Publication Date: 2021-12-01
• Subjects: power electronics -- multilevel inverter -- switched‐capacitor; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3191
• Languages: English
• ISSNs: 0098-9886

Abstract

Abstract: This paper proposes a basic asymmetric boost 35‐level inverter topology that can be extended to earn higher gains and levels. The proposed structure benefits from following advantages: extendibility, voltage boosting capability, natural voltage balancing of capacitors, low average voltage stress on semiconductors and large ratio of number of steps to components. The impulse charging current of capacitor(s) is suppressed by small inductor(s), which is bypassed by a diode during discharging mode. The low magnitude (accordingly small size, low price and low weight) and balanced output powers of V X and V Y sources are other important profits of proposed topology. The input DC sources can be realized by batteries or combination of PVs and dc–dc converters. This paper also proposes an algorithm for deciding the magnitude of DC sources, which maximizes the number of steps. The gain and steps can be further increased by adding more cascaded switched‐capacitor cells (CSCCs). Due to large number of levels, the output voltage quality of proposed structure is high, which helps to remove or downsize the ac‐side filter. The laboratory‐scaled prototype of converter (feeding a R – L load) has been implemented. The comparison and experimental results approve superiority and correct performance of proposed topology. Abstract : This paper proposes a basic asymmetric boost 35‐level inverter topology that can be extended to earn higher gains and levels. The proposed structure benefits from following advantages: extendibility, voltage boosting capability, natural voltage balancing of capacitors, low average voltage stress on semiconductors and large ratio of number of steps to components. The impulse charging current of capacitor(s) are suppressed by anti‐parallel inductor‐diode cells. The input DC sources can be realized by batteries or combination of PVs and dc‐dc converters. This paper also proposes an algorithm for deciding the magnitude of DC sources, which maximizes the number of steps. The gain and steps can be further increased by adding more cascaded switched‐capacitor cells (CSCCs). Due to large number of levels, the output voltage quality of proposed structure is high, which helps to remove or downsize the ac‐side filter. The comparison and experimental results approve superiority and correct performance of proposed topology. The low magnitude (accordingly small size, low price and low weight) and balanced output powers of level‐doubling sources ( V X, V Y ) are other important profits of proposed topology.