A high‐performance full swing 1‐bit hybrid full adder cell. Issue 3 (4th September 2021)

• Record Type: Journal Article
• Authors: Hussain, Shahbaz; Hasan, Mehedi; Agrawal, Gazal; Hasan, Mohd
• Is Part Of: IET circuits, devices & systems. Volume 16:Issue 3(2022)
• Page Start: 210
• Page End: 217
• Publication Date: 2021-09-04
• Subjects: 1‐bit adder -- FinFET -- full adder -- hybrid adder -- XOR‐XNOR; logic gates -- logic design -- adders -- carry logic -- SPICE -- performance evaluation; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/cds2.12097
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract: This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.