Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR. (May 2022) - Issartel, D.; Gao, S.; Pittet, P.; Cellier, R.; Golanski, D.; Cathelin, A.; Calmon, F.
Highlights: TCAD transient simulation for Single Photon Avalanche Diodes integrated in 28 nm FD-SOI CMOS technology. Unexpected behavior of the reference SPAD structure. Various approaches to improve SPAD FD-SOI behavior. Dark Count Rate improvement with optimizations of the SPAD structure. Abstract: This article presents a study of Single Photon Avalanche Diodes (SPAD) implemented in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology based on transient TCAD simulations and Dark Count Rate (DCR) measurements. The integration of SPAD in this technology is currently being studied. This work allows for a better understanding of the mechanism behind the quite high DCR measured at relative low excess bias voltages with the initial FD-SOI SPAD design (≈500 Hz/µm 2 at 5% excess bias voltage). In this study, a TCAD transient simulation methodology is introduced to better understand SPAD behavior during the avalanche process. TCAD simulations revealed that Shallow Trench Isolation (STI) structures within the active area have a negative effect on avalanche quenching, because of slower carrier evacuation with possible occurrence of secondary avalanches in series. Based on this analysis and on previous optimization works, we propose a new architecture of the FD-SOI SPAD combining several modifications to achieve a lower DCR (≈20 Hz/µm 2 at 5% excess bias voltage measured with passive quenching).