A 65nm/0.448 mW EEG processor with parallel architecture SVM and lifting wavelet transform for high-performance and low-power epilepsy detection. (May 2022) - Wen, Yongzhong; Zhang, Yuejun; Wen, Liang; Cao, Haojie; Ai, Guangpeng; Gu, Minghong; Wang, Pengjun; Chen, Huiling
Abstract: In recent years, low-power and wearable biomedical testing devices have emerged as a key answer to the challenges associated with epilepsy disorders, which are prone to crises and require prolonged monitoring. The feature vector of the electroencephalographic (EEG) signal was extracted using the lifting wavelet transform algorithm, and the hardware of the lifting wavelet transform module was optimized using the canonic signed digit (CSD) coding method. A low-power EEG feature extraction circuit with a power consumption of 0.42 mW was constructed. This article employs the support vector machine (SVM) technique after feature extraction to categorize and identify epilepsy. A parallel SVM processing unit was constructed to accelerate classification and identification, and then a high-speed, low-power EEG epilepsy detection processor was implemented. The processor design was completed using TSMC 65 nm technology. The chip size is 0.98 mm2, operating voltage is 1 V, operating frequency is 1 MHz, epilepsy detection latency is 0.91 s, power consumption is 0.448 mW, and energy efficiency of a single classification is 2.23 μJ/class. The CHB-MIT database test results show that this processor has a sensitivity of 91.86% and a false detection rate of 0.17/h. Compared to other processors, this processor is more suitable for portable/wearable devices. Highlights: This study implements a low-power feature extraction circuit based on the CSD coding technique and Db4 LWT algorithm. The parallel architecture of the classification unit is carried out using the serial-to-parallel conversion principle. Under the TSMC 65nm process, a 0.448mW low-power EEG epilepsy detection processor is implemented.