Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm. (9th March 2022)

• Record Type: Journal Article
• Authors: Kumar, N. Ashok; Shyni, G.; Peter, Geno; Stonier, Albert Alexander; Ganji, Vivekananda
• Other Names: Ravi Vinayakumar Academic Editor.
• Is Part Of: Wireless communications and mobile computing. Volume 2022(2022)
• Publication Date: 2022-03-09
• Subjects: Wireless communication systems -- Periodicals; Mobile communication systems -- Periodicals; 621.38205
• DOI: 10.1155/2022/4737569
• Languages: English
• ISSNs: 1530-8669

Abstract

Abstract : In the technical world, NoC (network-on-chip) is a noticeable communication subsystem based on integrated circuits. It is mainly used in improving the performance of system-on-chip (SoC) by bridging the intellectual properties in the SoCs. But there is a need of protected architecture which is dealing with routing and processing data in the multicore system-on-chip (SoC). The recent issue with the above is there is still a drawback in enabling a better network routing system for accessing physical networks. The methodology of NoC mainly depends on the routing scheme, switching techniques, and structuring topologies. In this paper, we propose a new technique in implementing the chip in order to maintain the data privacy of NoC routers. There are many works with different algorithms that were evolved in enabling the secureness of NoCs, but due to the key size and block size, it is still not able to reach the expected effectiveness. Our proposed work is intended in designing a NoC architecture by means of embedding advanced TACIT security algorithm in Virtex-5 FPGA. Here, we used a hash function which is under a 4 hash function (4-H) scheme. The main advantage of this key generation scheme is it is applicable for block size and key size up to 'n ' bit. Thus, this TACIT security algorithm enables 'n ' bit using the software VHDL programming language in Xilinx ISE 14.2 and Modelsim 10.1 b which are applicable for 1024 bit and 'N ' bits of block size on Virtex-5 FPGA systems. This design system can be enhanced by improving the factors like timing parameters, supporting memory, higher frequencies, and utilized summaries.