A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip design. (March 2022)

• Record Type: Journal Article
• Authors: Shanthi, J.; Rani, D. Gracia Nirmala; Rajaram, S.
• Is Part Of: Microelectronics journal. Volume 121(2022)
• Publication Date: 2022-03
• Subjects: C4.5 decision tree classification algorithm -- Machine learning -- Thermal-aware -- IR drop aware -- System-on-Chip -- Floorplanning -- B*tree -- Genetic algorithm -- Simulated annealing -- Island partitioning; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105361
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Aggressive scaling technology in deep sub-micron System-on-Chip (SoC) design brings various challenges to the Integrated Circuits (IC) designers. The significant challenges are temperature and voltage drop. Due to the increased intensity of circuits, the chip temperature increases tremendously, impacting the SoC performance and reliability. We propose a Machine Learning (ML) C4.5 Decision Tree (DT) classifier based floorplanning optimization algorithm to address these challenges in the early stage of IC design. Our algorithm aims to reduce the chip's peak and average temperatures, voltage drop, area and wirelength by means of a C4.5 DT based islanding technique. The proposed algorithm is a four-phase algorithm that includes, (i) Voltage assignment phase, (ii) C4.5 DT based island partitioning, (iii) Genetic Algorithm (GA) based island-level floorplanning, and (iv) Simulated Annealing (SA) based chip-level floorplanning. The island partitioning algorithm uses DT classification technique to classify the cores of the SoC into different islands, taking multiple features like area, power, and voltage of the blocks. Due to the intelligent DT algorithm that is used for the island classification, the run time is reduced to a great extent. We tested our algorithm on the famous floorplanning benchmark circuits, such as MCNC (Microelectronic Centre for North Carolina), and GSRC (Gigascale System Research Centre). The proposed algorithm produces a minimum of 23% and a maximum of 48% temperature reduction in various benchmark circuits. The proposed algorithm performed well and produced significant improvement on area, wirelength, temperature and IR drop simultaneously, when compared to other existing algorithms.